The invention relates to microwave synthesizers. In particular, the invention relates to a microwave synthesizer that has a dual YIG tuned oscillator.
Signal sources, sometimes referred to as frequency sources, are used to generate signals for use in many electronic systems. Signal sources can be divided into two main types known as the so-called xe2x80x9cfree-runningxe2x80x9d or xe2x80x9cunlockedxe2x80x9d sources and the xe2x80x9clockedxe2x80x9d or referenced sources. In general, there are two classes of unlocked signal sources: fixed frequency sources and tunable sources. Fixed frequency signal sources operate at a single frequency and can be made very stable, spectrally pure, and accurate by using so called high-Q resonators. High-Q resonator based sources include crystal oscillators, dielectric resonator oscillators, and surface acoustic wave (SAW) oscillators. While fixed frequency, high-Q resonator based sources offer high stability and state-of-the-art frequency accuracy, these high-Q resonator based sources generally produce a single, fixed frequency.
Tunable sources, on the other hand, provide an output that can be varied or tuned over a range of frequencies. The tunable sources are used in applications where the desired frequency is either unknown a priori during the system design or when the desired frequency must be changed or adjustable as a matter of system operation. Tunable sources usually provide continuous or nearly continuous tuning capability across their frequency range of operation. However, tunable sources generally exhibit poor frequency accuracy and frequency stability when compared to high-Q, fixed frequency sources. Therefore, when using unlocked sources for a given system design, a choice must usually be made between high stability, spectral purity, and accuracy on the one hand and frequency tunability on the other hand.
Applications requiring a source with both high-Q frequency stability/accuracy characteristics and frequency tunability generally necessitate the use of a so-called xe2x80x9clockedxe2x80x9d signal source. In a locked source, a tunable source is locked to or otherwise derived from a fixed or xe2x80x9creferencexe2x80x9d source. Often the tunable source is locked to a reference source using one or more feedback circuits or feedback loops. In the case of a locked source using a feedback loop, once the feedback loop is closed the tunable source can achieve frequency stability and accuracy that are a function of the reference source frequency stability. Such a configuration of tunable and fixed sources locked together is known in the art as a synthesized source or simply as a frequency synthesizer.
A frequency synthesizer, then, is a signal source that generates an output signal from one or more reference signals. In general, frequency synthesizers produce a signal consisting of a single frequency selected from among a finite set of discrete frequencies available by virtue of the design of the synthesizer. Frequency synthesizers of various forms and designs have been found to be highly useful if not essential in a wide variety of applications including FM car radios, sophisticated radar systems, and test equipment such as spectrum analyzers and signal generators.
In many cases, the synthesized signal produced by a given synthesizer is often at a higher frequency than that of the reference signal(s). The synthesized signal is typically a very stable, spectrally pure, single frequency signal having low or sometimes even very low phase noise. However, unlike other signal sources, such as a free-running voltage controlled oscillator (VCO), a given frequency synthesizer generally is capable of producing only a finite, although often large, number of selectable, discrete frequencies as an output signal. Therefore, frequency synthesizers are most often used where the frequency stability/precision and spectral purity are of paramount importance. Hereinbelow, frequency synthesizers will be referred to as variable frequency sources to distinguish them from the tunable, free-running sources that generally have a continuous tuning range.
A number of different types of frequency synthesizers or methods of frequency synthesis are known in the art including direct frequency generation, direct digital synthesis (DDS), and phase locked loop (PLL) frequency synthesis. The direct frequency generation synthesizer, while not strictly speaking considered a locked source, typically utilizes a combination of frequency multiplication, division, and addition to generate a desired frequency from one or more reference frequencies. Frequency multiplication is accomplished using a non-linear device, such as a step recovery diode or comb generator, to produce a large number frequency harmonics of a reference signal source frequency. Frequency division is typically accomplished using a digital frequency divider. Addition or subtraction of frequencies is implemented using a mixer, which ideally accepts two input signals and produces two output signals, one output signal at the frequency that is the sum of the two input signal frequencies and the other output signal at a frequency that is the difference of the two input signal frequencies. The combination of multiplication, addition, subtraction and division allows the direct frequency generation synthesizer to produce a finite number of output signal frequencies.
The DDS uses a digital to analog converter (DAC) to convert a digital data stream into an analog output signal. The digital data stream is a digital representation of a sampled version of the desired output signal, thus the DDS directly synthesizes the output signal. In a PLL synthesizer, a negative feedback loop is used to compare and xe2x80x9cphase lockxe2x80x9d the output signal of a tunable frequency source, such as a VCO, to a stable reference signal produced by one or more reference sources. When locked, the PLL output frequency is typically a multiple of the reference signal or linear combination of the reference signal and other signals generated by the synthesizer. There are also hybrid synthesizers that combine one or more of these or other various frequency synthesis approaches.
As is the case with frequency synthesizers in general, there are also many ways to realize a PLL synthesizer. In some applications, a simple single loop approach is acceptable or even preferred. In other instances, more complicated, multiple loop approaches are required. Generally, for high-performance applications, such as a local oscillator LO of a high-performance spectrum analyzer, the microwave synthesizer invariably involves multiple loops to optimize phase noise, spurious performance, sweep rate, and locking speed.
FIG. 1 illustrates a block diagram of a basic, single loop PLL synthesizer (SLS) used to synthesize a signal from a stable reference. The basic SLS comprises a voltage-controlled oscillator (VCO) 10, a loop frequency divider 16, a reference oscillator 18, a phase/frequency comparator or detector (PFD) 20, and a loop integrator 22. The VCO 10 produces an output signal, the frequency of which is proportional to an input control voltage. The frequency divider 16 to create a lower frequency signal divides the output signal produced by the VCO 10. The frequency divider 16 is an apparatus that accepts a signal at a frequency f and produces an output signal at a frequency f/N where N is the division factor of the frequency divider.
The signal produced by the frequency divider 16 is compared by the PFD 20 to a reference frequency signal produced by the reference oscillator 18. The PFD 20, in turn, produces an error voltage signal that is proportional to the phase/frequency difference between the frequency of the output signal of the frequency divider 16 and the reference signal frequency fref. The error voltage is integrated by the loop integrator 22 to produce the input control voltage of the VCO 10.
In some implementations, an output amplifier 12 and a loop amplifier 14 are included in the basic SLS. The output amplifier 12 is used to amplify the output signal produced by the SLS. The loop amplifier 14 is used to amplify the portion of the output signal that is used by the frequency divider 16. The loop amplifier 14 also provides reverse isolation between the frequency divider 16 and the SLS output.
The action of the negative feedback loop of the PLL eventually causes or forces the error voltage to equal zero, a situation that is strictly true only when the output from frequency divider 16 has the same phase as the reference signal fref In essence, the VCO 10 output signal is automatically adjusted by the feedback loop until the phase of the divided signal produced by the frequency divider 16 equals the phase of the reference signal. Moreover, since the frequency of a signal is the derivative of the phase of the signal, for a pair of signals to have the same phase the signals must also have the same frequency. When the error voltage has been made equal to zero by the action of the feedback loop, the loop is said to be xe2x80x9clockedxe2x80x9d to the reference source. When locked, the loop maintains the following frequency relationship:
f=N*frefxe2x80x83xe2x80x83(1)
Changing either the division factor N of the loop divider 16 or the reference signal frequency can be used to change the frequency f of the output signal. Generally but not always, the reference signal is fixed and the loop division factor is changed to affect tuning in a single loop frequency synthesizer (SLS).
The basic SLS has a major performance limitation when used to synthesize microwave frequencies in that the loop division factor N of the loop divider 16 is typically large. For example, if the frequency fref of the reference signal equals 5 MHz, N must be equal to 1000 in order to synthesize an output signal with a frequency f of 5000 MHz. Moreover, since by equation (1) the frequency f of the output signal equals N*fref when the loop is locked, one hertz of frequency noise at fref will produce N Hertz of frequency noise at the output signal frequency f A measure of phase noise that is added to the output signal from the reference source by the operation of a synthesizer is referred to as the noise gain or Gnoise of the synthesizer. In the SLS of FIG. 1, Gnoise is given in dB by
Gnoise=20*log(N) dBxe2x80x83xe2x80x83(2)
where log(xc2x7) is the logarithm, base ten of the argument. Again, by way of example, if the combined phase noise floor of the phase detector 20, the loop integrator 22, the loop divider 16, and the reference source 18 of the SLS is xe2x88x92150 dBc/Hz and N equals 1000, then the noise gain Gnoise is equal to 60 dB and the phase noise pedestal, which is the flat region of the phase noise inside the loop bandwidth, of the output signal would be at least xe2x88x9290 dBc/Hz.
Since low phase noise in the output signal is often a key performance characteristic of a synthesizer, it is important to consider approaches that minimize the phase noise. A microwave synthesizer, with its very high frequency operation and wide tuning range, typically requires special efforts to achieve good phase noise performance. Given that the phase noise in the single loop synthesizer is directly related to N, a seemingly obvious way to improve the phase noise is to reduce the division factor N. This can sometimes be accomplished in a satisfactory manner by increasing the reference signal frequency fref.
However, while it is always possible to increase the frequency fref to reduce N, there are limitations to this approach in terms of the practical reduction of phase noise. In particular, unless a fractional-N loop divider 16 (i.e. N not an integer) is used, the reference signal frequency fref entirely determines the spacing between adjacent frequencies f that can be synthesized. The spacing between adjacent frequencies f is often referred to as the xe2x80x9cstep sizexe2x80x9d or frequency resolution of the synthesizer. For example, if fref is 10 MHz and N is an integer, the minimum step size of the synthesizer is 10 MHz. While fractional-N dividers can be used to lessen the step size limitations of using higher reference frequencies, the current state-of-the-art in frequency divider technology limits fref of a fractional-N based PLL to about 50 MHz. In practice, a maximum fref limit of 10 MHz or below is more commonly employed with state-of-the-art, fractional-N dividers to minimize spurious problems associated with the dividers 16.
Moreover, even if step size is not a constraining factor, in general, the higher the possible frequency range of a given reference oscillator or reference source 18 technology, the higher the inherent phase noise produced by that oscillator 18 becomes. To put it another way, a high frequency, free-running, reference signal source generally has poorer phase noise performance than an equivalent low frequency free-running source due to the difficulty of obtaining resonators with sufficiently high-Q at high frequencies. Furthermore, the loop divider N operating at the higher frequency fref also produces higher noise. Therefore, increasing the frequency fref is usually not a practical approach for significantly reducing N and the phase noise gain associated therewith.
A more commonly employed technique to reduce N is to use a so-called offset loop synthesizer. FIG. 2 illustrates a block diagram of a basic offset loop frequency synthesizer (OLS). The OLS uses a low-noise, high frequency offset signal to downconvert or frequency shift the output signal of a main loop to a lower frequency prior to dividing the signal frequency in the main loop divider. The OLS comprises a VCO 10, an offset mixer 24, an offset signal source 26, a loop frequency divider 16, a PFD 20, a reference source 18, and a loop integrator 22.
The output signal of the VCO 10 at a frequency f is mixed with an offset signal at a frequency fos. Generally, the offset signal frequency fos is chosen to be close to the output signal frequency f. The offset mixer 24, in turn, ideally produces output signals with the sum and the difference of the two input frequencies. The difference frequency is used to produce an intermediate frequency (IF) signal at a frequency fif where the value of the frequency fif is given by:
|fif|=|fxe2x88x92fos|xe2x80x83xe2x80x83(3)
The difference signal is selected by using a lowpass filter 28 and becomes the filtered IF signal. The filtered IF signal is then divided by the loop frequency divider 16 and compared to the reference signal from the reference source 18 by the PFD 20 to produce an error voltage that is integrated by the loop integrator 22 to produce the VCO 10 control voltage. Typically, an output amplifier 12 and a loop amplifier 14 are used in the OLS, as mentioned above for the SLS.
When the loop is locked, the output signal frequency is equal to (fosxe2x88x92N*fref) or (fos+N*Fref), depending the polarity of the loop. Since the IF signal is at a frequency fif that is typically much lower than the VCO 10 output signal frequency f, the division factor N required for a given reference signal frequency fref is typically much smaller than would be required for the SLS described hereinabove with respect to FIG. 1. Therefore, the phase noise gain Gnoise associated with the loop division factor N is significantly reduced using an offset loop as in the OLS.
For example, consider the synthesis of an output signal at f=5000 MHz from a reference signal of fref=5 MHz using an offset signal frequency fos equal to either at 4995 MHz or 5005 MHz. In this example N is set equal to 1, resulting in a Gnoise=0 dB. Comparing this result to the single loop, SLS example hereinabove where N=1000, it is readily apparent that the offset loop synthesizer (OLS) has up to 60 dB less Gnoise than the single loop synthesizer (SLS).
The difficulty encountered with using an offset loop synthesizer (OLS) approach to meet low phase noise specifications involves the problem of producing a low phase noise offset signal at approximately the same frequency as the output signal. Advantageously, however, the offset signal generally does not need to have as fine a frequency resolution as that of the OLS output signal, although it typically needs to have the same frequency range as the output signal. In fact, in some applications where the output frequency range is limited, a fixed frequency offset signal will suffice. Even when several offset signal frequencies are desired, the opportunity exists to use a much coarser resolution for the offset signal. This fact opens up the possibility of using a second phase locked loop for generating the offset signal and employing a higher frequency reference signal for this loop.
A side benefit of using an offset loop approach based on a PLL loop synthesized offset signal is that the overall tuning range of the synthesizer can be extended by changing the division factors and/or reference signal frequency fref used in both the main loop and the offset loop. For example, the offset loop can provide the synthesizer with large or course frequency steps while the main loop provides the fine frequency resolution.
This range extension concept is illustrated in FIG. 3 as a frequency plot showing, for example, three bands labeled A, B, and C. Each step of the offset loop course tuning range sets or selects the operational range of the synthesizer to be in one of the bands, A, B, or C. Once the operational band has been set, the synthesizer then tunes across the selected operational band, for example band B, using the fine frequency steps of the main loop. The fine-tuning frequency steps of the main loop provide tuning from a lower end of the selected band at frequency flB to an upper end of the band at frequency fuB. Each band has a corresponding lower and upper band edge. For example, band A has a lower band edge at frequency flA and an upper band edge at fuA.
Extremely broad tuning ranges with very fine frequency resolution are possible with this approach. The caveat is that the span or tuning range covered by the IF signal must be wide enough to cover the xe2x80x9cgapsxe2x80x9d or frequency range between the coarse frequency steps. In practice the main loop is designed to have a range that overlaps or is greater than the spacing between the coarse frequency steps. Referring to the example of FIG. 3, this overlap is indicated by the region of the frequency bands labeled xe2x80x9cfoxe2x80x9d.
When using two PLLs, one as the main loop and one in the offset signal loop, it is often important to consider the added cost of the offset PLL. A conventional low cost technique to produce the offset signal via a PLL is to use a sampler 30 driven by a low frequency sampling signal. FIG. 4 illustrates a block diagram of such an implementation of a dual loop synthesizer (DLS) comprising the main loop and an offset loop.
Typical microwave samplers 30 comprise a pair of sampling diodes and use a step recovery diode driven by a sampling source to produce fast pulses that momentarily turn on the pair of sampling diodes at the sample frequency fs. When the sampling diodes turn xe2x80x98onxe2x80x99, they sample the VCO 10 output signal. The effect of this sampling is to produce a multitude of signals at the output of the sampler 30 that are the sum and the difference of the harmonics of the frequencies f and fs, (i.e. |J*fs+/xe2x88x92K*f|). The sampler 30 as employed in the sampling offset loop synthesizer illustrated in FIG. 4 thus behaves as a harmonic mixer. Only one of the mixing products from the sampler 30, typically |fxe2x88x92H*fs| is selected as the sampler IF signal for locking purposes.
It should be noted that the low frequency sampling signal must have exceptionally low phase noise to produce a low phase noise, synthesized output signal. This is because the phase noise of the signal produced by the sampling offset loop approach is the power sum of the phase noise of the VCO output signal and the phase noise of the sampling signal multiplied by the harmonic number H.
In addition, in sampler based synthesizers so-called crossing spurs may be a problem. In a synthesizer in which sampler IF signals cover a wide range of frequencies, nth order mixing products may fall inside the same frequency range as that of the sampler IF signal. These mixing products are generally unwanted and therefore spurious signals. Spurious signals resulting from nth order mixing products tend to move in frequency as the synthesizer is tuned, at a rate that is n times that of the desired, 1st order product. These spurs tend to cross the desired operational band, and are therefore referred to as crossing spurs. Unfortunately, since these nth order mixing products share the frequency range with that of the sampler IF signal, they cannot be filtered out using a filter.
While crossing spurs cannot be eliminated, the detrimental effect of crossing spurs can be reduced by decreasing the sampler IF signal frequency range. The narrower the frequency range of the sampler IF signal, the higher will be the order of the spurs that will cross the operational band of the sampler IF signal. Advantageously, the higher the order of a spur, the lower the amplitude of the spur and therefore, the less detrimental it is in terms of synthesizer performance.
Unfortunately, reducing the frequency range of the sampler IF signal for a given synthesizer design requires a larger selection of sample frequencies fs to minimize the sample frequency fs gaps. The frequency range of the sample frequency fs is generally determined by the minimum output frequency and the minimum sample frequency fs used. The maximum frequency gap that the sampler IF signal must cover is determined by the step size of sample frequency fs and the highest harmonic of the sample frequency fs being utilized. So there may be severe practical limitations on how narrow the sampler IF can be made in a given design.
Consequently, there are a number of conflicting requirements for the sampler-based PLL synthesizer. Compromises are often made to balance the requirements of the sample frequency fs and sampler IF signal range. The sampler 30 output or sampler IF signal frequency range needs to be as small as possible to help to reduce the effect of crossing spurs and to simplify the requirements of the tuning reference or interpolation signal of the main loop. However, the frequency range of the sampler IF signal needs to be as large as possible to allow for a coarse stepped sample frequency fs. The coarser the frequency steps, the easier and less expensive it is to implement the sampling signal. The sampling signal should have a high frequency sampling signal frequency fs to minimize the harmonic number H. However, a small H requires the sample frequency fs to have a wider frequency range, making low phase noise more difficult to achieve. Moreover, the power level of the signal entering the sampler 30 should be as high as is practical to produce the strongest sampler output signal and maximize the signal-to-noise ratio (SNR) of that signal. Maximizing the sampler 30 output SNR helps to minimize the phase noise of the sampler. On the other hand, the signal level into the sampler 30 should be as low as possible to minimize the generation of higher harmonics and thus to minimize power level of the crossing spurs.
Slightly better performance can be achieved by using a comb generator and an offset mixer in place of the sampler 30. The comb generator is usually a step recovery diode driven hard by the sampling signal to produce a strong comb signal with good signal-to-noise ratio. The comb generator output is used as an RF input into the offset mixer with the VCO output signal acting as an LO input. It is known in the art that using a high-level mixer as the offset mixer with strong LO drive produces an IF signal with minimum spurs. In addition, a filter can be inserted between the comb generator and the offset mixer to further improve spur performance. The comb generator and offset mixer can achieve much lower phase noise than a sampler. However, the dominant phase noise contributor in the offset PLL synthesizer is the phase noise pedestal of the offset signal as noted hereinabove. Therefore, the phase noise improvements that may be gained from the use of the comb generator and offset mixer are likely to be modest. It is also possible to achieve minor improvements in the offset signal phase noise pedestal by using multiple dividers. For example, using two ECL phase detectors and two ECL dividers in parallel can reduce the phase noise due to these components by about 3 dB. Even with these minor improvements, it is difficult to achieve a phase noise pedestal ofxe2x88x92125 dBc/Hz for a conventional tunable offset PLL based microwave synthesizer.
Accordingly, it would be advantageous to have a microwave synthesizer apparatus that achieved a wide tuning range, small step size and low phase noise. In addition, it would be desirable to minimize the DC power requirements and the overall factory cost. In the case of a local oscillator for a spectrum analyzer, the LO synthesizer must be sweepable or variable in narrow spans and preferably in wide spans as well. Such a microwave synthesizer apparatus would solve a long-standing need in the area of microwave signal synthesis.
The present invention provides a novel dual Yttrium-Iron-Garnet (YIG) tuned oscillator (YTO) microwave synthesizer apparatus. The dual YTO microwave synthesizer features very low phase noise, fine frequency resolution and wide tuning range coverage. The microwave synthesizer of the present invention utilizes a single frequency offset signal source in an offset phase lock loop (PLL) to translate the output signal Fout to a lower IF signal Fif for locking to a low frequency interpolation signal Fint. The use of the single fundamental offset source instead of the conventional multiple harmonic offset signal from a comb generator or sampler results in superior phase noise and spurious performance. Furthermore, the use of a dual YTO by the synthesizer of the present invention minimizes overall cost and power consumption of the synthesizer by combining the dual YTO, comprising a main YTO and an offset YTO, in a single package.
In one aspect of the present invention, the dual YTO microwave synthesizer comprises a main PLL and an offset PLL. The offset PLL produces a single frequency offset signal Fos that is used to offset or downconvert a synthesizer output signal Fout. The offset signal Fos eliminates the need for a loop divider in the main loop and the related phase noise degradation associated therewith. Moreover, the use of the single frequency offset signal Fos eliminates low-order crossing spurs in the output signal Fout of the microwave synthesizer. Furthermore, the tunable high-frequency sampling PLL that is a major phase noise contributor in conventional offset PLL-based microwave synthesizers is replaced with a fixed frequency sampling signal Fs, which can be built as a crystal oscillator with very low phase noise. The power consumption of this fixed frequency Fs can be significantly lower than the tunable sampling PLL using ECL devices, which generally require much higher power. By combining the offset YTO in the same package of the main YTO so that only one main coil is used, no additional main coil power is required. The power requirement and cost for this dual YTO would only be slightly more than that of a single YTO. Thus, the cost and power consumption of the dual YTO microwave synthesizer of the present invention can be reduced compared to conventional synthesizers while achieving significant performance improvements.
In another aspect of the invention, the dual YTO microwave synthesizer is provided with a mode selection feature. The mode selection feature selects between operating the main loop in an offset or dual loop mode and a variable divider or single loop mode. The offset mode provides low phase noise while the divider mode provides faster tuning speed and wider tuning range.
In yet another aspect of the present invention, the dual YTO microwave synthesizer is provided having an offset signal with a smaller step size by using a selectable frequency divider. The selectable frequency divider utilizes the fixed frequency, sampling signal Fs. The sampling signal Fs provides sampling of the offset signal Fos as well as being divided and mixed to produce a selectable reference signal to which the sampled offset signal is phase locked.